The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to an interconnect structure that contains a metallic blocking layer which prevents ion flow of interconnect metals to enable acceptable electromigration performance. The present application also relates to a method of forming such an interconnect structure.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure, which may also be referred to as an interconnect structure, typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
As the interconnect structure feature sizes shrink, it is necessary to scale barrier (e.g., TaN) thickness in order to maximize Cu volume and to enable a low line and via resistance. Scaling sidewall barrier thickness allows maximization of Cu volume in interconnect structures, and scaling barrier thickness at the via bottom allows reduction of via resistance.
Reliability, in particular electromigration performance, is negatively impacted as the diffusion barrier thickness is scaled. In addition to risks associated with diffusion barrier continuity on sidewalls, discontinuities in the diffusion barrier at the via bottom can lead to breakdown of the “short-length” criterion. This criterion requires blocking of Cu ion flow at the via bottom in order to prevent massive Cu migration from level to level. Hence, there is a need for providing an interconnect structure containing no diffusion barrier, yet containing a means for blocking Cu ion (or other metallic ion) migration from one level to another level.